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december 2004 copyright ? alliance semiconductor. all rights reserved. as7c33128ft32b 3.3v 128k 32/36 flow through synchronous sram ? 12/10/04; v.1.1 alliance semiconductor p. 1 of 19 as7c33128ft36b features ? organization: 131,072 words 32 or 36 bits ? fast clock to data access: 6.5/7.5/8.0/10.0 ns ?fast oe access time: 3.5/4.0 ns ? fully synchronous flow through operation ? asynchronous output enable control ? available in 100-pin tqfp package ? individual byte write and global write ? multiple chip enables for easy expansion ? 3.3v core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? linear or interleaved burst control ? snooze mode for reduced power standby ? common data inputs and data outputs selection guide ?65 -75 -80 -10 units minimum cycle time 7.5 8.5 10 12 ns maximum clock access time 6.5 7.5 8.0 10.0 ns maximum operating current 250 225 200 175 ma maximum standby current 120 100 90 90 ma maximum cmos standby current (dc) 30 30 30 30 ma logic block diagram q0 q1 128k 32/36 memory array burst logic clk clr ce address dq ce clk dq d clk dq byte write registers register dq c clk dq byte write registers dq b clk dq byte write registers dq a clk dq byte write registers enable clk dq register enable clk dq delay register ce output buffer input registers power down dq[a:d] 4 36/32 19 17 19 19 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe zz lbo oe clk 36/32 36/32 a [18:0]
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 2 of 19 as7c33128ft36b 4 mb synchronous sram products list 1,2 1 core power supply: vdd = 3.3v + 0.165v 2 i/o supply voltage: vddq = 3.3v + 0.165v for 3.3v i/o vddq = 2.5v + 0.125v for 2.5v i/o pl-scd : pipelined burst synchronous sram - single cycle deselect pl-dcd : pipelined burst synchronous sram - double cycle deselect ft : flow-through burst synchronous sram ntd 1 -pl : pipelined burst synchronous sram with ntd tm ntd-ft : flow-through burst synchronous sram with ntd tm org part number mode speed 256kx18 as7c33256pfs18b pl-scd 200/166/133 mhz 128kx32 as7c33128pfs32b pl-scd 200/166/133 mhz 128kx36 as7c33128pfs36b pl-scd 200/166/133 mhz 256kx18 as7c33256pfd18b pl-dcd 200/166/133 mhz 128kx32 as7c33128pfd32b pl-dcd 200/166/133 mhz 128kx36 as7c33128pfd36b pl-dcd 200/166/133 mhz 256kx18 as7c33256ft18b ft 6.5/7.5/8.0/10 ns 128kx32 as7c33128ft32b ft 6.5/7.5/8.0/10 ns 128kx36 as7c33128ft36b ft 6.5/7.5/8.0/10 ns 256kx18 as7c33256ntd18b ntd-pl 200/166/133 mhz 128kx32 as7c33128ntd32b ntd-pl 200/166/133 mhz 128kx36 as7c33128ntd36b ntd-pl 200/166/133 mhz 256kx18 as7c33256ntf18b ntd-ft 6.5/7.5/8.0/10 ns 128kx32 as7c33128ntf32b ntd-ft 6.5/7.5/8.0/10 ns 128kx36 as7c33128ntf36b ntd-ft 6.5/7.5/8.0/10 ns 1. ntd: no turnaround delay. ntd tm is a trademark of alliance semiconducto r corporation. all trademar ks mentioned in this do cument are the property of their respective owners.
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 3 of 19 as7c33128ft36b pin arrangement dqp c /nc dq c0 dq c1 v ddq v ssq dq c2 dq c3 dq c4 dq c5 v ssq v ddq dq c6 dq c7 nc v dd nc v ss dq d0 dq d1 v ddq v ssq dq d2 dq d3 dq d4 dq d5 v ssq v ddq dq d6 dq d7 dqp d /nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp b /nc dq b7 dq b6 v ddq v ssq dq b5 dq b4 dq b3 dq b2 v ssq v ddq dq b1 dq b0 v ss zz dq a7 dq a6 v ddq v ssq dq a5 dq a4 dq a3 dq a2 v ssq v ddq dq a1 dq a0 dqp a /nc lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bw d bw c bw b bw a ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a nc vdd a tqfp 14 20 mm note: pins 1,30,51,80 are nc for 32
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 4 of 19 as7c33128ft36b functional description the as7c33128ft32b/36b is a high-performance cmos 4-mbit synchronous static random ac cess memory (sram) device organized as 131,072 words 32 or 36 bits. fast cycle times of 7.5/8.5/10/ 12 ns with clock access times (t cd ) of 6.5/7.5/8.0/10 ns. three chip enable (ce ) inputs permit easy memory expansion. burst operation is ini tiated in one of two ways: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent internal ly generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address cloc ked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation, the data accessed by the current address registered in the address registers by the positive edge of clk are carried to the data-out buf fer. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low and both addr ess strobes are high. burst m ode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use an interl eaved count sequence. with lbo driven low, the device uses a linear count sequence. write cycles are performed by di sabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 32/36 regardless of the st ate of individual bw[a:d] inputs. alternat ely, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signals. bwn is ignored on the clock edge that samples adsp low, but it is sampled on all subsequent cl ock edges. output buffers are disabled when bwn is sampled low regardless of oe . data is clocked into the da ta input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp are as follows: ?adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ?we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip enable ce0 blocks adsp , but not adsc . the as7c33128ft32b and as7c33128ft36b family operates from a core 3.3v power supply. i/ os use a separate power supply that can operate at 2.5v or 3.3v. these devices are available in a 100-pin tqfp package. tqfp capacitance *guaranteed not tested tqfp thermal resistance parameter symbol test conditions min max unit input capacitance c in * v in = 0v - 5 pf i/o capacitance c i/o * v out = 0v - 7 pf description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled test conditions follow sta ndard test methods and procedures for measurin g thermal impedance, per eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 5 of 19 as7c33128ft36b signal descriptions snooze mode snooze mode is a low current, power-dow n mode in which the device is dese lected and current is reduced to i sb2 . the duration of snooze mode is dictated by the length of time the zz is in a high state. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. after entering snoo ze mode, all i nputs except zz is disabled and all outputs go to high-z. any operation pending when entering snooze mode is not guaranteed to successfully com plete. therefore, snooze mode (read or write) must not be ini tiated until valid pending operations are completed. similarly, when exit ing snooze mode during t pus , only a deselect or read cycle s hould be given while the sram is transitioning out of snooze mode. pin i/o properties description clk i clock clock. all inputs except oe , zz, and lbo are synchronous to this clock. a,a0,a1 i sync address. sampled when all chip enables are active and when adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and when oe is active. ce0 i sync master chip enable. sample d on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the ?synchron ous truth table? for more information. ce1, ce2 i sync synchronous chip enables, active high, and active low, respectively. sample d on clock edges when adsc is active or when ce0 and adsp are active. adsp i sync address strobe processor. asserted low to load a new a ddress or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe i sync global write enable. assert ed low to write all 32/36 bits. when high, bwe and bw[a:d] control write enable. bwe i sync byte write enable. asserted low with gwe high to enable effect of bw[a:d] inputs. bw[a,b,c,d] i sync write enables. used to control wr ite of individual bytes when gwe is high and bwe is low. if any of bw[a:d] is active with gwe high and bwe low, the cycle is a write cycle. if all bw[a:d] are inactive, the cycle is a read cycle. oe i async asynchronous output enable . i/o pins are driven when oe is active and chip is in read mode. lbo istatic selects burst mode. when tied to v dd or left floating, device follows interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. zz i async snooze. places device in low power mode; data is reta ined. connect to gnd if unused. nc - - no connect
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 6 of 19 as7c33128ft36b asynchronous truth table notes: 1. x means ?don?t care? 2. zz pin is pulled down internally 3. for write cycles that follows read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 4. snooze mode means power down state of which st and-by current does not depend on cycle times 5. deselected means power down state of whic h stand-by current depends on cycle times burst sequence table write enable truth table (per byte) 1 1 key: x = don?t care, l = low, h = high, n = a, b, c, d; bwe , bwn = internal write signal. function gwe bwe bwa bwb bwc bwd write all bytes lxxxxx hlllll write byte a hllhhh write byte c and d hlhhll read hhxxxx hlhhhh operation zz oe i/o status snooze mode h x high-z read l l dout l h high-z write l x din, high-z deselected l x high-z interleaved burst address (lbo = 1) linear burst address (lbo = 0) a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 1 st address 0 00 11 01 1 1 st address 0 00 11 01 1 2 nd address 0 10 01 11 0 2 nd address 0 11 01 10 0 3 rd address 1 01 10 00 1 3 rd address 1 01 10 00 1 4 th address 1 11 00 10 0 4 th address 1 11 00 11 0
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 7 of 19 as7c33128ft36b synchronous truth table [4] ce0 1 1 x = don?t care, l = low, h = high ce1 ce2 adsp adsc adv write [2] 2 for write , l means any one or more byte write enable signals (bwa , bwb , bwc or bwd ) and bwe are low or gwe is low. write = high for all bwx , bwe , gwe high. see "write enable trut h table (per byte)," on pa ge 6 for more information. oe address accessed clk operation dq hxxxlx x x na l to h deselecthi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read q l h l l x x x h external l to h begin read hi ? z l h l h l x h l external l to h begin read q l h l h l x h h external l to h begin read hi ? z xxxhhl h l next l to hcontinue readq xxxhhl h h next l to hcontinue readhi ? z xxxhhh h l current l to hsuspend readq xxxhhh h h current l to hsuspend readhi ? z hxxxhl h l next l to hcontinue readq hxxxhl h h next l to hcontinue readhi ? z hxxxhh h l current l to hsuspend readq hxxxhh h h current l to hsuspend readhi ? z l h l h l x l x external l to h begin write d 3 3 for write operation following a read, oe must be high before the input data set up time and held high throughout the input hold time 4 zz pin is always low. xxxhhl l x next l to hcontinue writed hxxxhl l x next l to hcontinue writed xxxhhh l x current l to hsuspend writed hxxxhh l x current l to hsuspend writed
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 8 of 19 as7c33128ft36b note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only and functional operation of the device at these or any other con- ditions outside those indicated in the opera tional sections of this specification is not implied. exposure to absolute maximum rating conditions may affect reliability. recommended operating conditions at 3.3v i/o recommended operating conditions at 2.5v i/o absolute maximum ratings parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 c temperature under bias t bias ?65 +135 c parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 3.135 3.3 3.465 v ground supply vss 0 0 0 v parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 9 of 19 as7c33128ft36b dc electrical characteristics for 3.3v i/o operation dc electrical characteristics for 2.5v i/o operation ? lbo and zz pins have an internal pull- up or pull-down, and input leakage = 10 a. * v ih max < vdd +1.5v for pulse width less than 0.2 x t cyc ** v il min = -1.5 for pulse width less than 0.2 x t cyc i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 2* v dd +0.3 v i/o pins 2* v ddq +0.3 input low (logic 0) voltage v il address and control pins -0.3** 0.8 v i/o pins -0.5** 0.8 output high voltage v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? v output low voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 v parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7* v dd +0.3 v i/o pins 1.7* v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3** 0.7 v i/o pins -0.3** 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym conditions -65 -75 -80 -10 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 250 225 200 175 ma standby power supply current i sb all v in 0.2v or > v dd ? 0.2v, deselected, f = f max , zz < v il 120 100 90 90 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 30 30 30 30 i sb2 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 30 30 30 30
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 10 of 19 as7c33128ft36b snooze mode electrical characteristics timing characteristics over operating range parameter sym ?65 -75 -80 ?10 unit notes 1 1 see ?notes? on page 16. min max min max min max min max cycle time t cyc 7.5 ? 8.5 ? 10 ? 12 ? ns clock access time t cd ? 6.5 ? 7.5 ? 8.0 ? 10 ns output enable low to data valid t oe ? 3.5 ? 3.5 ? 4.0 ? 4.0 ns clock high to output low z t lzc 2.5 ? 2.5 ? 2.5 ? 2.5 ? ns 2,3,4 data output invalid from clock high t oh 2.5 ? 2.5 ? 2.5 ? 2.5 ? ns 2 output enable low to output low z t lzoe 0 ? 0 ? 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.0 ? 3.5 ? 4.0 ? 5.0 ns 2,3,4 clock high to output high z t hzc ? 3.0 ? 3.5 ? 4.0 ? 5.0 ns 2,3,4 output enable high to invalid output t ohoe 0?0?0? 0 ? ns clock high pulse width t ch 2.5 ? 3.0 ? 4.0 ? 4.0 ? ns 5 clock low pulse width t cl 2.5 ? 3.0 ? 4.0 ? 4.0 ? ns 5 address setup to clock high t as 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6 data setup to clock high t ds 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6 write setup to clock high t ws 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6,7 chip select setup to clock high t css 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6,8 address hold from clock high t ah 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6 adsp setup to clock high t adsps 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6 adsc setup to clock high t adscs 1.5 ? 2.0 ? 2.0 ? 2.0 ? ns 6 adv hold from clock high t advh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 description conditions symbol min max units current during snooze mode zz > v ih i sb2 30 ma zz active to input ignored t pds 2cycle zz inactive to input sampled t pus 2cycle zz active to snooze current t zzi 2cycle zz inactive to exit snooze current t rzzi 0
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 11 of 19 as7c33128ft36b key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:d] is don?t care. don?t care falling input rising input undefined t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe t css t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states a2 a1 a3 dout q(a2y10) q(a2y11) q(a3) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) t hzc t lzoe t csh read q(a1) suspend read q(a1) read q(a2) burst read q(a 2y01 ) read q(a3) dsel burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 ) t oe ce1
as7c33128ft32b ? 12/10/04; v.1.1 alliance semiconductor p. 12 of 19 as7c33128ft36b timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe din t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d] read q(a1) suspend write d(a1) read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write d(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write d(a 2y11 ) adv burst write d(a 3y10 )
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 13 of 19 as7c33128ft36b timing waveform of read/write cycle (adsp controlled; adsc high) note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address bwe ce0 , ce2 adv oe din dout t cd t advh t lzoe t oe t lzc q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read q(a 3y01 ) suspend read q(a 3y11 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3) bw[a:d]
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 14 of 19 as7c33128ft36b timing waveform of read/write cycle(adsc controlled, adsp = high) note: adv is don?t care here. t cyc t ch t cl t adsch clk adsc address a2 a1 t adscs a3 a4 a6 a5 a7 a8 a9 t ah t as bwe t wh t ws t csh ce0 ,ce2 t css t lzoe t oe t hzoe q(a1) q(a2) q(a3) q(a4) q(a9) q(a10) t cd t oh d(a6) d(a7) d(a5) t ds t dh oe dout din read q(a1) read q(a2) read q(a3) read q(a4) write d(a5) write d(a6) write d(a7) write d(a8) read q(a10) ce1 a10 d(a8) read q(a9) bw[a:d]
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 15 of 19 as7c33128ft36b timing waveform of power down cycle t cyc t ch t cl t adsps clk adsp a ddress a1 t adsps a2 bwe t wh t ws t csh ce0 ,ce2 t css adv t lzoe t oe t hzoe q(a1) q(a2) oe dout din adsc t hzc t pds sleep zz setup cycle t pus zz recovery cycle n ormal operation mode ce1 zz q(a2( y 01)) bw[a:d] read q(a1) read q(a1y01) read q(a2) read q(a2y01) state t zzi i sb2 t rzzi i supply
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 16 of 19 as7c33128ft36b ac test conditions z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc , see figure c. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v an d 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v. v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o 353 ? / 1538? 5 pf* 319 ? / 1667? d out gnd figure c: output load (b) *including scope and jig capacitan c thevenin equivalent: +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o notes 1 for test conditions, see ac test conditions , figures a, b, c. 2 this parameter measured with ou tput load condition in figure c. 3 this parameter is sampled, but not 100% tested. 4t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temperature and voltage. 5 tch measured as high above vih and tcl measured as low below vil. 6 this is a synchronous device. all addresses must meet the speci fied setup and hold times for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all ri sing edges of clk when chip is enabled. 7 write refers to gwe , bwe , bw[a:d]. 8 chip select refers to ce0 , ce1 , ce2
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 17 of 19 as7c33128ft36b package dimensions 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.85 16.15 he 21.80 22.20 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters he e hd d b e a1 a2 l1 l c
? as7c33128ft32b 12/10/04; v.1.1 alliance semiconductor p. 18 of 19 as7c33128ft36b note: add suffix ?n? to the above part numbers for lead free parts (ex. as7c33128ft32b-65tqcn) 1. alliance semiconductor sram prefix 2. operating voltage: 33 = 3.3v 3. organization: 128 = 128k 4. flowthrough mode 5. organization: 32 = x32; 36 = x36 6. production version: b= product revision 7. clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0] 8. package type: tq = tqfp 9. operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 10. n = lead free part ordering information package width ?65 -75 ?80 ?10 tqfp x32 as7c33128ft32b- 65tqc as7c33128ft32b- 75tqc as7c33128ft32b- 80tqc as7c33128ft32b- 10tqc tqfp x32 as7c33128ft32b- 65tqi as7c33128ft32b- 75tqi as7c33128ft32b- 80tqi as7c33128ft32b- 10tqi tqfp x36 as7c33128ft36b- 65tqc as7c33128ft36b- 75tqc as7c33128ft36b- 80tqc as7c33128ft36b- 10tqc tqfp x36 as7c33128ft36b- 65tqi as7c33128ft36b- 75tqi as7c33128ft36b- 80tqi as7c33128ft36b- 10tqi part numbering guide as7c 33 128 ft 32/36 b ?xx tq c/i x 123 4 5678910
as7c33128ft32b ? ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respecti ve companies. alliance reserve s the right to make changes to this document and its products at any time without notice. alliance assumes no respon sibility for any errors that ma y appear in this document. the data contained herein represents allianc e's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product desc ribed herein is under development, signif icant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potentia l customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or cust omer. alliance does not assume any responsi bility or liability arising out of the app lication or use of any product described herein, and disclaims an y express or implied warranties related to the sa le and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringe ment of any intellectual property rights, except as express ag reed to in alliance's terms and conditions of sale (which are available fr om alliance). all sales of alliance products are made exclusively according to allian ce's terms and conditions of sale. the purchase of products from allianc e does not convey a license under any pate nt rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant in jury to the user, and the inclusion of all iance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all clai ms arising from such use. alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c33128ft32b as7c33128ft36b document version: v.1.1 ? as7c33128ft36b

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